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Data Sheet No. PD60224 Rev.A
IRMCK201
High Performance Configurable Digital AC Servo Control IC
Features
* * * * * * * * * * * * *
Complete closed loop current control (Synchronously Rotating Frame Field Orientation) Versatile Space Vector PWM Direct interface to IR2175 current sensing high voltage IC Direct Encoder interface with multiplexed/nonmultiplexed Hall A/B/C signals Direct interface to IR213x 3-phase gate driver IC Closed loop velocity control
Product Summary
Max. Clock Input (Sysclk) Max. PLL clock for current feedback 33.3 MHz 133.3 MHz
Closed loop current control computation time 6 sec max Closed loop current loop bandwidth (-3 dB) Closed loop velocity loop update rate PWM carrier frequency 5.5 kHz 5 / 10 kHz 83.3 kHz max 12 bit calibrated 8 MHz
PWM counter resolution Configurable architecture o Supports AC PM motor or Induction motor Current feedback temp drift/offset o Closed loop or open loop control
Asynchronous serial communication interface (RS232C, RS422) Fast SPI interface 4 channel 12-bit A/D interface with simultaneous sample/hold 8-bit parallel bus interface for microcontroller expansion (supports most 8-bit microprocessors) Integrated brake IGBT control ServoDesignerTM (Configuration Tool) available
Max SPI clock Package: QFP100
Description
IRMCK201 is a complete AC servo motor control IC. It contains closed loop current control for sinusoidal AC current, and closed loop velocity control based on encoder position feedback interface. A standard communication port is provided for RS232C or RS422, in addition to a fast SPI communication interface. Unlike a traditional DSP or a microcontroller, the IRMCK201 does not require any programming effort to complete the complex control algorithm. It allows users to configure the algorithm for specific application needs. Permanent magnet motor or AC induction motor are supported. IRMCK201 facilitates high performance servo design together with the IR2175 current sensing IC and IR213x high voltage 3-phase gate driver IC, which simplifies the hardware design while minimizing cost. For multi-axis applications, IRMCK201 can be used as a multi-drop slave drive based on the SPI protocol. The package is available in a 100-pin QFP.
IRMCK201 Overview
IRMCK201 is a new International Rectifier integrated circuit device designed as a one-chip solution for complete closed loop current control and velocity control for a high performance servo drive system. Unlike a traditional microcontroller or DSP, IRMCK201 does not require any programming to complete complex AC servo algorithm development. Combined with International Rectifier's high voltage gate drive and current sensing IC, the user can implement a complete AC servo control with minimum component count and virtually no design effort. Although IRMCK201 contains dedicated logic to perform closed loop control of AC current and velocity, it has a wide range of application coverage through its flexible configuration ability. The drive can be easily configured for induction machine closed loop vector control or permanent magnet motor servo drive. Rich motion peripherals, analog and digital I/O can also be configured. Host communication logic contains an asynchronous RS232C or RS422 communication interface, a fast slave SPI interface and an 8-bit-wide Host Parallel Interface. All communication ports have the same access capability to the host register set. The user can write to and read from the predefined registers to configure and monitor the drive through these communication ports.
IRMCK201 Main Features
IRMCK201 contains the following functions for AC servo motor control applications: * * * * * * * * * * * * * * * * * * * * * * * * * Complete closed loop current control based on Synchronously Rotating Frame Field Orientation Configurable update rate with PWM carrier frequency Configurable parameters (all PI controller gains, PI output limit range, current feedback scaling, encoder feedback scaling) Configurable control structure for Induction machine or AC Permanent Magnet machine (Disable/enable slip gain) Closed loop velocity control with configurable update rate Enable/disable velocity loop Selectable reference input for torque and speed input Analog reference input RS232C/RS422 reference input Dynamic braking control for excess DC bus voltage Cycle-by-cycle on/off Control for Brake IGBT DC bus voltage feedback Standard Encoder interface with Hall ABC support A/B quadrature signal input up to 1 MHz Choice of separate or multiplexed Hall A/B/C signal input Auto-initialization with Hall A/B/C plus Z pulse input Adaptable for any line count encoder from 200 PPR to 10,000 PPR 1/T counter (2 MHz) for low speed performance improvement Space Vector PWM with deadtime insertion IR2175 current sensing IC interface IR213x high voltage gate driver IC interface Low cost serial 12 bit A/D interface with multiplexer and sample/hold circuit 4 channel analog output by PWM 0-3.3 V, 120 kHz output. EEPROM for startup initialization of internal data/parameters through host register interface AT24C01A, 128 x 8 Versatile host communication interface
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IRMCK201
RS232C or RS422 host interface Fast SPI slave host interface with multi-drop capability Parallel Host interface (total 12 pins) Multiplexed data/address bus Address Enable RD/WR Discrete I/O Start (Input) Stop (Input) IFBCAL (Input) Fault Clear (Input) Fault (Output) SYNC (Output) PWM Active (Output) LED Two-bit bi-color
*
*
*
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IRMCK201 Table of Contents
Overview .......................................................................................................................................................................... 2 IRMCK201 Main Features ............................................................................................................................................ 2 IRMCK201 Block Diagrams .......................................................................................................................................... 7 Basic Block Diagram .................................................................................................................................................... 7 Detailed Block Diagram................................................................................................................................................ 8 Input/Output of IRMCK201 .......................................................................................................................................... 9 Typical Application Connections................................................................................................................................. 13 IC Crystal Clock Circuitry .......................................................................................................................................... 14 Low Pass Filter............................................................................................................................................................ 15 Implementing the Low Pass Filter Shield ............................................................................................................... 16 Cp Rp and Cs Component Values........................................................................................................................... 16 PLL Reset.................................................................................................................................................................... 16 DC Electrical Characteristics and Operating Conditions ......................................................................................... 17 Absolute Maximum Ratings........................................................................................................................................ 17 Recommended Operating Conditions ......................................................................................................................... 17 DC Characteristics ...................................................................................................................................................... 18 Common Quiescent and Leakage Current .................................................................................................................. 18 Input Characteristics - Non Schmitt Trigger Inputs ................................................................................................... 18 Input Characteristics - Schmitt Trigger Inputs ........................................................................................................... 18 Output Characteristics................................................................................................................................................. 18 Pin and I/O Characteristic Table ................................................................................................................................. 19 Power Consumption .................................................................................................................................................... 21 AC Electrical Characteristics and Operating Conditions ......................................................................................... 22 System Level AC Characteristics................................................................................................................................ 22 Sync Pulse to Sync Pulse Timing............................................................................................................................ 22 FAULT and REDLED Response to GATEKILL ................................................................................................... 23 Host Interface AC Characteristics............................................................................................................................... 24 SPI Timing .............................................................................................................................................................. 24 Host Parallel Timing ................................................................................................................................................... 25 Host Parallel Read Cycle......................................................................................................................................... 25 Host Parallel Write Cycle........................................................................................................................................ 26
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IRMCK201
Discrete I/O Electrical Characteristics ........................................................................................................................ 27 Motion Peripheral Electrical Characteristics............................................................................................................... 28 PWM Electrical Characteristics .............................................................................................................................. 28 IR2175 Interface ..................................................................................................................................................... 28 Encoder Electrical Characteristics........................................................................................................................... 29 Analog To Digital Interface Electrical Characteristics ............................................................................................... 30 ADC Timing............................................................................................................................................................ 30 PLL Interface Electrical Characteristics...................................................................................................................... 32 Appendix A Host Register Map................................................................................................................................ 33
Host Parallel Access................................................................................................................................................ 33 SPI Register Access ................................................................................................................................................ 33 RS-232 Register Access.......................................................................................................................................... 33 Write Register Definitions .......................................................................................................................................... 38 QuadratureDecode Register Group (Write Registers)............................................................................................. 38 PwmConfig Register Group (Write Registers) ....................................................................................................... 39 CurrentFeedbackConfig Register Group (Write Registers) .................................................................................... 40 SystemControl Register Group (Write Registers)................................................................................................... 41 CurrentLoopConfig Register Group (Write Registers) ........................................................................................... 42 VelocityControl Register Group (Write Registers)................................................................................................. 43 FaultControl Register Group (Write Registers) ...................................................................................................... 45 SVPWMScaler Register Group (Write Registers) .................................................................................................. 45 DiagnosticPwmControl Register Group (Write Registers) ..................................................................................... 46 SystemConfig Register Group (Write Registers).................................................................................................... 47 DirectHostVoltageControl Register Group (Write Registers) ................................................................................ 47 32bitQuadDecode Register Group (Write Registers).............................................................................................. 48 EepromControl Registers (Write Registers)............................................................................................................ 49 HallSensorEncoderInit (Write Registers - EEPROM only) ................................................................................... 50 Read Register Definitions ........................................................................................................................................... 51 QuadratureDecodeStatus Register Group (Read Registers).................................................................................... 51 SystemStatus Register Group (Read Registers) ...................................................................................................... 51 DcBusVoltage Register Group (Read Registers) .................................................................................................... 52 FocDiagnosticData Register Group (Read Registers)............................................................................................. 52 FaultStatus Register Group (Read Registers).......................................................................................................... 54 VelocityStatus Register Group (Read Registers) .................................................................................................... 54 CurrentFeedbackOffset Register Group (Read Registers) ...................................................................................... 55 32bitQuadDecodeStatus Register Group (Read Registers)..................................................................................... 55 EepromStatus Registers (Read Registers)............................................................................................................... 56 FOCDiagnosticDataSupplement Register Group (Read Registers) ........................................................................ 57 Appendix B Appendix C Package .................................................................................................................................................. 58 Errata .................................................................................................................................................... 60
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IRMCK201 List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Basic Block Diagram of IRMCK201.............................................................................................................. 7 Detailed Block Diagram of IRMCK201 ......................................................................................................... 8 Input/Output of IRMCK201 ........................................................................................................................... 9 Typical Connection of IRMCK201 .............................................................................................................. 13 Oscillator Circuit .......................................................................................................................................... 14 PLL Low Pass Filter Shielding..................................................................................................................... 15 System Level SYNC-to-SYNC Timing........................................................................................................ 22 FAULT and REDLED Response to GATEKILL......................................................................................... 23 SPI Timing.................................................................................................................................................... 24 Host Parallel Read Cycle Timing ............................................................................................................... 25 Host Parallel Write Cycle Timing .............................................................................................................. 26 Discrete I/O Timing.................................................................................................................................... 27 PWM Timing .............................................................................................................................................. 28 IR2175 Interface ......................................................................................................................................... 28 Encoder Timing .......................................................................................................................................... 29 Top Level ADC Timing.............................................................................................................................. 30 ADC Specific Timing ................................................................................................................................. 31
List of Tables
Table 1: Typical Values for the Clock Circuit ................................................................................................................ 14 Table 2: PLL Test Pin Assignments................................................................................................................................ 15 Table 3: PLL Low Pass Filter Values ............................................................................................................................. 16 Table 4: Absolute Maximum Ratings ............................................................................................................................. 17 Table 5: Recommended Operating Conditions ............................................................................................................... 17 Table 6: DC Characteristics ............................................................................................................................................ 18 Table 7: Non Schmitt Trigger Input Characteristics ....................................................................................................... 18 Table 8: Schmitt Trigger Input Characteristics ............................................................................................................... 18 Table 9: Output Characteristics....................................................................................................................................... 18 Table 10: Pin and I/O Characteristics ............................................................................................................................. 21 Table 11: IRMCK201 Power Consumption.................................................................................................................... 21 Table 12: System Level SYNC-to-SYNC Timing .......................................................................................................... 23 Table 13: FAULT and REDLED Response to GATEKILL ........................................................................................... 23 Table 14: SPI Timing ...................................................................................................................................................... 24 Table 15: Host Parallel Read Cycle Timing.................................................................................................................... 25 Table 16: Host Parallel Write Cycle Timing................................................................................................................... 26 Table 17: Discrete I/O Timing ........................................................................................................................................ 27 Table 18: PWM Timing .................................................................................................................................................. 28 Table 19: IR2175 Interface ............................................................................................................................................. 28 Table 20: Encoder Timing .............................................................................................................................................. 29 Table 21: Top Level ADC Timing.................................................................................................................................. 30 Table 22: ADC Specific Timing ..................................................................................................................................... 31 Table 23: PLL Electrical Characteristics......................................................................................................................... 32 Table 24: QFP100 Package............................................................................................................................................. 58 Table 25: QFP100 Dimensions ....................................................................................................................................... 59
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IRMCK201 IRMCK201 Block Diagrams
Basic Block Diagram
Figure 1 shows the basic block diagram of the IRMCK201 surrounded by various Accelerator ICs. Host communications are provided over SPI, RS-232C or Host parallel ports. Two current sensing ICs (IR2175) and a three phase high voltage gate drive typically implement the high voltage / current interface between the IRMCK201 IC and motor. The IRMCK201 can operate in a "stand-alone" mode without the host controller. utilized to load motor-specific parameters into the IC. A serial EEPROM could be
AC Power
EEPROM
iMOTION Chip Set
TM
Analog Speed Reference
IRMCK201
Multi-Axis Host or other host controller
RS232C or RS422 Host Register Interface DC bus dynamic brake control
select
A/D interface
BRAKE
A/D
MUX
DC bus feedback
+ -
+ + -
IGBT module
IRAMX16UP60A IR2136
SPI Interface
e
dt +
j
Space Vector PWM
Dead time
FAULT
Parallel Interface
Configuration Registers Monitoring Registers
Ks
+
e
j
2/3
Period/Duty counters Period/Duty counters
IR2175 IR2175
1/T counter speed measurement
Quadrature Decoding
Encoder
Motor
Figure 1.
Basic Block Diagram of IRMCK201
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IRMCK201
Detailed Block Diagram
Figure 2 shows a detailed block diagram or the IRMCK201. All logic and algorithms are pre-programmed, and the user does not need to make any effort to develop code, alleviating the tedious design process. If needed, the user can configure the drive to tailor the control per specific needs to meet the required specification. This configuration is easily done by accessing the host register set through the communication interface.
Closed Loop Velocity Control, Sequencing Control Update Rate = PWM carrier frequency / 2
EXT_REF
I1 x I2 O I1 I3 I3 I2
REF scale 4096
Closed Loop Current Control Update Rate = PWM carrier frequency x1 or x 2
DCV_FDBK Feedforward path enable VQLIM - VQLIM 2 Optional Current Sense
2 MUX 8 channel Serial A/D Interface
+/-16383 = +/-max_speed
INT_VQ SPDKI SPDKP INT_REF Reference Select Velocity Control Enable
ADS7818 A/D interface DC bus dynamic brake control
CNVST CLK DATA
BRAKE
CURKI IQREF CURKP
+
RAMP
GSenseL ModScl GSenseU VQS 6
START STOP DIR FLTCLR SYNC FAULT PWM ACTIVE RCV SND RTS CTS
+
-
PI
+
IDREF
-
PI
+
VQ
Sequence Control
IQLIMAccel Rate Decel Rate IQLIM+
+
PI INT_VD - VDLIM VDLIM Slip gain 4096
VD
e
+
j
VDS
Space Vector PWM
Dea d time
Gate Signals
FAULT
VD enable Slip gain enable
PWMmode 2Pen Dtime PWMen AngleScale MaxEncCount SpdScale InitZval 3 Encoder A/B/Z Encoder Hall A/B/C
RS232C/ RS422 Interface
I2
Configuration Registers
Host Register Interface
I1
I1 x I2 I3
I3 O
dt
0
+
Quadrature Decoding
3 4096 EncType InitZ Optional CurrentSense Zpol
SCK SDO SDI CS
SPI Slave Interface
IQ scale
Data Address Control
17
Parallel Interface
Monitoring Registers
IQ
I2 O
I1 x I2 I3
I3 I1
ID
O I2
I1 x I2 I1 I3 I3
4096
e
j
IV
2/3
IR2175 interface IR2175 interface
Current Offset W Current Offset V
Motor Phase Current V Motor Phase Current W
IW
ID scale
Communication Modules
+/-16383 = +/-4X of rated current for IQ +/-4095 = +/-rated ID for IM field flux
INT_DAC1 INT_DAC2 INT_DAC3 INT_DAC4
DAC_PWM1
4ch DAC module
DAC_PWM2 DAC_PWM3 DAC_PWM4
Figure 2.
Detailed Block Diagram of IRMCK201
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IRMCK201
Input/Output of IRMCK201
Figure 3 shows the interface signals divided into sub-groups. For detailed pin assignment, please refer to Table 10 in this data sheet.
SYSCLK RESETN XPD
PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL BRAKE GATEKILL
PLL & System Clock
BYPASSMODE BYPASSCLK OSC1CLK OSC2CLK PLLTEST CHGO LPVSS
PWM gate signal Interface
IFB0 SCLK MISO MOSI CSN ENA ENB ENZ HALLA HALLB HALLC IFB1
IR2175 Interface
Host Communication Interface
HPOEN HPWEN HPD[0-7] HPA HPCSN TX RX BAUDSEL SYNC
Encoder Interface
IRMCK201
ADCLK ADOUT ADCOVST ADMUX0 ADMUX1
A/D Interface
START
Discrete I/O
STOP IFBCAL FLTCLR PWMACTIVE FAULT
RESSAMPLE
REDLED GREENLED
LED
Serial EEPROM
SCA SCL
PID[0-1]
POWER ID
Figure 3.
Input/Output of IRMCK201
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IRMCK201
Host Interface Group
Signal SCLK MISO MOSI CSN HPOEN HPWEN HPD [7:0] HPA HPCSN TX RX BAUDSEL SYNC Input (I) / Output (O) I O I I I I I/O I I O I I O Low (L) / High (H) True Asserted Positive edge sensitive L L L H L H L Function SPI clock Master input and slave output Master output and slave input SPI chip select Parallel data output enable Parallel data write cycle identification Parallel data Parallel data address cycle identification Chip select RS-232 data out RS-232 data in RS-232 baud rate: 0 = 57,600; 1 = 1,031,250 bps Start of PWM cycle
Discrete I/O Group
Signal IFBCAL START STOP FLTCLR PWMACTIVE FAULT Input (I) / Output (O) I I I I O O Low (L) / High (H) True Asserted H H H H H H Function Current offset calibration signal Start command Stop command Fault clear command PWM state Fault state
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IRMCK201
Motion Peripheral Group
Signal PWMUH PWMUL PWMVH PWHVL PWMWH PWMWL BRAKE GATEKILL IFB0 IFB1 ENA ENB ENZ HALLA HALLB HALLC Input (I) / Output (O) O O O O O O O I I I I I I I I I Low (L) / High (H) True Asserted Varies, Based on Write Register 0x0D L Varies, Based on Write Register 0x0C Bit 7 Function PWM phase U high side PWM phase U low side PWM phase V high side PWM phase V low side PWM phase W high side PWM phase W low side IGBT gate When asserted, negates all six PWM signals, host writeable Channel 0 (phase V) Channel 1 (phase W) Encoder A Encoder B Encoder Z Hall A Hall B Hall C
Analog Interface Group
Signal ADCLK ADOUT DAC [3:0] ADCONVST ADMUX0 ADMUX1 Input (I) / Output (O) O I O O O O Low (L) / High (H) True Asserted Negative Edge Sensitive L H H Function Clock to ADS7818 Serial data from ADS7818 Diagnostic DAC Conversion start to ADS7818 Analog input mux select Analog input mux select
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IRMCK201
PLL Interface Group
Signal XPD RESETN BYPASSCLK BYPASSMODE OSC1CLK OSC2CLK PLLTEST CHGO LPVSS Input (I) / Output (O) I I I I I I I I/O I/O Low (L) / High (H) True Asserted L L H H H Function PLL reset Digital logic reset Internal test pin - force to logic low Internal test pin - force to logic low 33.33 MHz crystal input 33.33 MHz crystal input Internal test pin - force to logic low Low pass filter Low pass filter ground
Miscellaneous Group
Signal SD SCA SCL PID[0:1] GREENLED REDLED Input (I) / Output (O) O I/O O I O O Low (L) / High (H) True Asserted Varies, Based on Write Register 0x0C Bit 1 Positive Edge Sensitive H H Function Shut down, host writeable EEPROM data EEPROM clock Power ID to SystemStatus register, host readable LED signal LED signal
Power Supply Group
Signal LVDD AVCC MVDD VSSHC Function IC Logic +3.3V power supply IC Analog +3.3V power supply IC Phase +3.3V Lock Loop power supply IC Phase Lock Loop power supply return
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IRMCK201 Typical Application Connections
Typical application connection is shown in Figure 4. In order to complete a high performance servo drive control, all necessary components are shown in connection to IRMCK201.
System Clock
33MHz Crystal SYSCLK SCLK MISO MOSI CSN TX RX PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL BRAKE GATEKILL FAULTCLR BAUDSEL Isolator Isolator Isolator Isolator Isolator Isolator Isolator Isolator Isolator
SPI Interface
5V
To PC RS232C
MAX232A
Gate Drive or Intelligent IGBT power module (IRAMX16UP60A)
Optional Microcontroller
8051 uP
PARALLEL DATA CONTROL SIGNALS
5V IFB0 Isolator 5V PO
IR2175 IR2175
Motor Current Sensing
Input Switches
START STOP IFBCAL FLTCLR PWMACTIVE SYNC
IFB1
Isolator
PO
Anaog reference input DC bus voltage
IRMCK201
Serial EEPROM Bi-Color LED
AT24C01A
SCA SCL REDLED GREENLED PID[0-1]
ADCLK ADOUT ADCONVST
ADS7818 4052
1/4
4066
1/4
Optional Current sensing Optional Current sensing
4066
ADMUX0 ADMUX1 RESSAMPLE
HALLA HALLB HALLC
ENA ENB ENZ
DS3486 Encoder Interface DS3486 DS3486
Analog Output
DAC0 DAC1 DAC2 DAC3
Figure 4.
Typical Connection of IRMCK201
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IRMCK201
IC Crystal Clock Circuitry
The clock input to the IC is a 33.33 MHz crystal oscillator. required to terminate the crystal to the IC. Two shunt capacitors and possibly a series resistor is
The values of the R/C will vary based on actual PCB attributes, and some empirical analysis may be required to get the PLL to start oscillating. Once oscillating, verify that the signal waveforms at the OSC1CLK and OSC2CLK pins are sinusoidal rather than trapezoidal. Refer to Table 1 for suggested R/C values. Most low-cost crystals can be used in this application. An example is a Citizen Part number CM309B33.333MABJT available from Digi-Key under part number 300-4160-1-ND.
OSC1CLK
IRMCK201
C1 XTAL R2 OSC2CLK R1 C2
Figure 5.
Oscillator Circuit
Component XTAL C1 C2 R1 R2
Value 33.33 5 5 0 3.9K
Units MHz pF pF
Table 1: Typical Values for the Clock Circuit
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IRMCK201
PLL Clock Circuitry
The IRMCK201 contains a PLL that creates a 2X and 4X clock from the input 33.33 MHz input clock pin. There are a number of pins on the IC allocated for factory testing purposes, which need to be left unconnected. Table 2 shows required PCB signal connections for these pins. Note that N/C is for factory use only. Pin Number 1 2 7 15 16 17 18 23 24 25 41 45 56 89 PCB Connection VSS VSS VSS N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
Table 2: PLL Test Pin Assignments
Low Pass Filter
The low pass filter for this PLL resides between the CHGO and LPVSS pins. Three passive components are required to implement this filter: Cp, Rp and Cs. Figure 6 shows how to place these components around the IC. A shield should be placed below Rp, Cp and Cs made out of copper etch.
Shielded by LPVSS CHGO
Rp IRMCK201 Cs
Cp
LPVSS
Figure 6.
PLL Low Pass Filter Shielding
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IRMCK201
Implementing the Low Pass Filter Shield
Make all connections between CHGO, Rp, Cp, Cs and LPVSS as short as possible. Create the underlining shield by "copper filling" a larger area in the signal plane of the PCB. Connect this shield to the LPVSS pin of the IC. Do not connect this shield to signal ground (VSS).
Cp Rp and Cs Component Values
For a typical FR4 PCB, the values of the passive components are shown in Table 3.
Component Rp Cp Cs
Value 3.9K 1000 Not Installed
Units pF -
Table 3: PLL Low Pass Filter Values
PLL Reset
There are two reset pins on the IC, XPD and RESETN both low true. XPD holds the PLL circuitry in reset when low. Upon XPD going high, the PLL circuitry begins to lock onto the 33.33 MHz clock input. The PLL circuit may take up to 1 ms to become stable. RESETN asserted low holds the internal DSP logic in reset. Upon RESETN going high, the IC digital logic becomes active. RESETN should be held low during and at least 1 ms after XPD goes high false to hold the internal DSP logic in reset while the PLL becomes stable.
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IRMCK201 DC Electrical Characteristics and Operating Conditions
Absolute Maximum Ratings
Note: VSS = 0 Volt PARAMETER Power Supply Voltage Input Voltage Output Voltage Output Current per Pin Storage Temperature SYMBOL VDD VI VSS-0.3 to 7 VO IOUT Tstg VSS-0.3 to VDD+0.5 +/- 30 -65 to 150 V V mA C LIMITS VSS-0.3 to 4.0 VSS-0.3 to VDD+0.5 UNIT S V V Non 5 Volt Tolerant Pins Only on 5 Volt Tolerant Pins NOTE
Table 4: Absolute Maximum Ratings
Recommended Operating Conditions
Note: VSS = 0 Volt PARAMETER Power Supply Voltage Input Voltage Ambient Temperature SYMBOL VDD VI Ta MIN 3.0 VSS -40 TYP 3.3 MAX 3.6 VDD 5.5 85 UNITS V V V C Non 5 Volt Tolerant Pins Only on 5 Volt Tolerant Pins Note 1 NOTE
Table 5: Recommended Operating Conditions
Notes: 1. The ambient temperature range is recommended for Tj = -40 to 125 C
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IRMCK201
DC Characteristics Common Quiescent and Leakage Current
PARAMETER Quiescent Current Input Leakage Current SYMBOL IDDS CONDITIONS VI=VDD or VSS VDD=MAX IOH=IOL=0 Ta=Tj=85C VDD=MAX VIH=VDD VIL=VSS MIN TYP MAX 0.35 UNITS uA
ILI
-1
-
1
uA
Table 6: DC Characteristics
Input Characteristics - Non Schmitt Trigger Inputs
PARAMETER High Level Input Voltage Low Level Input Voltage SYMBOL VIH1 VIL1 CONDITIONS VDD=MAX VDD=MIN MIN 2.0 TYP MAX 0.8 UNITS V V
Table 7: Non Schmitt Trigger Input Characteristics
Input Characteristics - Schmitt Trigger Inputs
PARAMETER High Level Input Voltage Low Level Input Voltage Hysteresis Voltage SYMBOL VT1+ VT1VH1 CONDITIONS VDD=MAX VDD=MIN VDD=MIN MIN 1.1 0.6 0.1 TYP MAX 2.4 1.8 UNITS V V V
Table 8: Schmitt Trigger Input Characteristics
Output Characteristics
PARAMETER High Level Output Voltage Low Level Output Voltage SYMBOL VOH3 VOL3 CONDITIONS VDD=MIN IOH=-12mA VDD=MIN IOH = 12mA MIN VDD - 0.4 TYP MAX VSS + 0.4 UNIT S V V
Table 9: Output Characteristics
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IRMCK201
Pin and I/O Characteristic Table
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name BYPASSMODE BYPASSCLK OSC1CLK LVDD OSC2CLK VSS PLLTEST XPD VSSHC MVDD VSSHC AVDD CHGO LPVSS N.C. (CLKI) N.C. (CLKSEL) N.C. (CPT0) N.C. (CPT1) LVDD REDLED GREENLED VSS N.C. (TSTCLK) N.C. (TSTSEL) N.C. (OLAP) PWMWL PWMWH PWMVL LVDD PWMVH PWMUL VSS PWMUH BRAKE RESETN FLTCLR GATEKILL IFB0 IFB1 SD 20K -120K Pull Up 20K -120K Pull Up 20K-120K Pull Down INTERNAL IC RESISTOR TERMINATION 40K-240K Pull Down 40K-240K Pull Down Pin Type I I I P O P I I P P P P O P I I I I P O O P I I I O O O P O O P O O I O I I I O 5.50 VOLT TOLERANT INPUT YES YES INPUT DC CHARACTERISTIC TABLE Table 8 Table 8 Table 7 Table 7 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 OUTPUT DC CHARACTERISTIC TABLE Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9
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19
IRMCK201
Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Pin Name N.C. (D0) PID0 PID1 LVDD N.C. (D3) CSN VSS MOSI MISO SCLK TX RX BAUDSEL LVDD ADMUX0 N.C. (N2) VSS ADMUX1 RESSAMPLE ADCONVST ADCLK ADOUT SYNC FAULT START STOP IFBCAL FLTCLR LVDD PWMACTIVE DAC[3] VSS DAC[2] DAC[1] DAC[0] HPD[0] HPD[1] HPD[2] VDD 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Up 20K -120K Pull Up INTERNAL IC RESISTOR TERMINATION Pin Type I I I P I I P I O I O I I P O I P O O O O I O O I I I I P O O P O O O B B B P 5.50 VOLT TOLERANT INPUT YES YES YES YES YES YES YES YES YES YES INPUT DC CHARACTERISTIC TABLE Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 7 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 7 Table 7 Table 7 OUTPUT DC CHARACTERISTIC TABLE -
Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 -
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IRMCK201
Pin Number 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name HPD[3] HPD[4] VSS HPD[5] HPD[6] HPD[7] HPOEN HPWEN HPA N.C. (N11) HPCSN ENCZ ENCB ENCA LVDD HALLC HALLB VSS HALLA SCL SDA 20K -120K Pull Up 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down INTERNAL IC RESISTOR TERMINATION 20K -120K Pull Down 20K -120K Pull Down Pin Type B B P B B B I I I I I I I I P I I P I O B 5.50 VOLT TOLERANT INPUT YES YES YES YES YES YES YES YES YES YES INPUT DC CHARACTERISTIC TABLE Table 7 Table 7 Table 7 Table 7 Table 7 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 7 OUTPUT DC CHARACTERISTIC TABLE Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9
Table 10: Pin and I/O Characteristics
Power Consumption
PARAMETER PTotal SYMBOL PTOTAL CONDITIONS VDD=3.3V MIN TYP 0.927 MAX UNITS WATT
Table 11: IRMCK201 Power Consumption
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21
AC Electrical Characteristics and Operating Conditions
System Level AC Characteristics
Sync Pulse to Sync Pulse Timing
-5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
t3 SYNC t1 SAMPLE DELAY END OF PROCESSING WAIT FOR NEXT SYNC PULSE t2
SPEED LOOP
CURRENT REGULATOR
SPACE VECTOR MODULATION
Critical Path Timing Including PWM Calculation Time
Figure 7. System Level SYNC-to-SYNC Timing
SYMBOL t1 t2
t3
DESCRIPTION Current Feedback Sample Delay from SYNC Pulse Falling Edge Closed Loop Computation Time (current control only including PWM computation) Closed Loop Computation Time (current and velocity control including PWM calculation time) Minimum SYNC-to-SYNC time (current control only including PWM calculation time) Minimum SYNC-to-SYNC time (current and velocity control including PWM calculation time)
TIME 4.32 6.33
UNITS s s
7.68 10.65 s 12.0
Table 12: System Level SYNC-to-SYNC Timing
FAULT and REDLED Response to GATEKILL
GATEKILL FAULT REDLED FLTCLR t1 t2
t3
t4
Figure 8.
FAULT and REDLED Response to GATEKILL
SYMBOL t1 t2 t3 t4
DESCRIPTION FAULT Response to GATEKILL REDLED Response to GATEKILL FAULT Response to FLTCLR REDLED Response to FLTCLR
TYP 685 715 145 175
UNITS ns ns ns ns
Table 13: FAULT and REDLED Response to GATEKILL
IRMCK201
Host Interface AC Characteristics
SPI Timing
tSCLK SCLK
CS
tCSS tMOSIS
MOSI
MISO tMISO tMISOZ
Figure 9.
SPI Timing
SYMBOL fSCLK tSCLK tCSS tMOSIS tMISO tMIOZ
DESCRIPTION SPI Clock Frequency SPI Clock Period CS to SCLK high Setup MOSI to SCLK low Setup SCLK to MISO Valid CS to MOSI High Impedance
MIN 125 20 20 30 15
MAX 8
35
UNITS MHz ns ns ns ns ns
Table 14: SPI Timing
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24
IRMCK201
Host Parallel Timing
Host Parallel Read Cycle
HPCSN tHPCSN
HPWEN
tHPWENS tHPA tAHPD
HPA
tHPAS
HPD[7:0] tHPOENS HPOEN tHPOENH
tHPZD tHPOEN
VALID tHPDZ
Figure 10.
Host Parallel Read Cycle Timing
SYMBOL tHPCSN tHPWENS tHPAS tAHPD THPZD tHPDZ tHPOENH tHPOENS tHPOEN
DESCRIPTION HPCSN Period HPWENS Setup HPA Setup HPD [7:0] Access HPD [7:0] Active HPD [7:0] High Impedance HPOEN Hold HPOEN Setup HPOEN Period
MIN 70 10 10 60 0 0 10 10 70
MAX
105 9 6
UNIT S ns ns ns ns ns ns ns ns ns
NOTE
Note 3 Note 3
Table 15: Host Parallel Read Cycle Timing
Note: 3. HPOEN must be stable before and after the high to low transition of HPCSN.
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IRMCK201
Host Parallel Write Cycle
tHPCSN
HPCSN tHPWENS tHPAS HPA
tHPA
HPWEN
tHPWEN
HPD[7:0] tHPD[7:0]S HPOEN tHPOENS
tHPD[7:0]
tHPOEN
Figure 11.
Host Parallel Write Cycle Timing
SYMBOL tHPCSN tHPWENS tHPWEN tHPAS tHPA tHPD[7:0] tHPOENS tHPOEN
DESCRIPTION HPCSN Period HPWENS Setup HPWEN Period HPA Setup HPA Period HPD[7:0] Setup HPOEN Setup HPOEN Period
MIN 70 10 70 -10 70 -10 10 70
UNITS ns ns ns ns ns ns ns ns
NOTE
Note 4
Table 16: Host Parallel Write Cycle Timing
Note: 4.
HPOEN must be asserted high while HPCSN low during a Host Parallel Write Cycle.
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IRMCK201
Discrete I/O Electrical Characteristics
IFBCAL START STOP FLTCLR GATEKILL
tL
Discrete I/O Timing
Figure 12.
SYMBOL tL
DESCRIPTION Pulse Width IFBCAL Pulse Width START Pulse Width STOP Pulse Width FLTCLR Pulse Width GATEKILL
MIN 100 100 100 1 490
UNITS ms ns ns us ns
Table 17: Discrete I/O Timing
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27
IRMCK201
Motion Peripheral Electrical Characteristics
PWM Electrical Characteristics
tDEADTIMERESOLUTION SYNC PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL tDEADTIMERESOLUTION
Figure 13.
PWM Timing
SYMBOL tDEADTIMERESOLUTION
DESCRIPTION Deadtime Insertion Logic Resolution
Table 18: PWM Timing
VALUE 30
UNITS ns
IR2175 Interface
tIFB tIFBH IFB0 IFB1 tIFBL
Figure 14.
IR2175 Interface
SYMBOL fIFB tIFB tIBH tIFBH
DESCRIPTION Current Feedback Input Frequency Current Feedback Period Current Feedback High Pulse Width Current Feedback Low Pulse Width
MIN 95 10.52 500 ns 500 ns
MAX 165 6.06 10 us 10 us
UNITS kHz s
Table 19: IR2175 Interface
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IRMCK201
Encoder Electrical Characteristics
Table 20 shows the input timing characteristics of the encoder inputs. Please refer to the IRMCK201 Application Developer's Guide for an example encoder input circuit that drives the IRMCK201.
tENCODER tENCH ENA ENB ENZ
tENCL
HALLA HALLB HALLC RESETN
VALID tHALLABCS
Figure 15.
Encoder Timing
SYMBOL fENCODER tENCODER tENCL tENCH tHALLABCS
DESCRIPTION Encoder Input Frequency ENA ENB ENZ Period ENA ENB ENZ Pulse Width ENA ENB ENZ Pulse Width HALLA HALLB HALLC Setup to RESETN
MIN 1 500 500 1
TYP
MAX 1
UNITS MHz s ns ns s
Table 20: Encoder Timing
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29
Analog To Digital Interface Electrical Characteristics
ADC Timing
System Level Timing The IRMCK201 contains logic to drive an ADC Converter, Analog MUX and associated Sample and Hold circuits. Figure 16 and Table 21 show the system level timing of these elements. Figure 17 and Table 22 show specific timing parameters associated with the ADC Converter. Refer to the Application Developers Guide for a detailed description of ADC, MUX and Sample and Hold signal system level protocol. The IRMCK201 ADC interface has been designed for interfacing to the Burr-Brown ADS7818 ADC and Texas Instruments CD4052 MUX.
tSYNC
SYNC RESSAMPLE ADCONVST ADMUX0 ADMUX1 ADCLK
tADCONVST
tADMUX
tADMUX1S
tADCLK
tADCLK
Figure 16.
Top Level ADC Timing
SYMBOL tSYNC tRESSAMPLES tADMUX0S tADMUX1S tADCONVSTS
DESCRIPTION SYNC Pulse Width SYNC Falling Edge to RESSAMPLE Valid ADCONVST to ADMUX0 Valid ADCONVST to ADMUX1 Valid ADCONVST to ADCLK
MIN -10 40 40 71
TYP 3
MAX 10 61 61 91
UNITS s ns ns ns ns
Table 21: Top Level ADC Timing
IRMCK201
Converter Level Timing
t1 ADCLK tADOUTS ADOUT t2 ADCONVST D11 tHADOUT D10 D2 D1 D0 tADCLK
RESSAMPLE t3 ADMUX0
ADMUX1
Figure 17.
ADC Specific Timing
SYMBOL fADCLK tADCLK t1 t2 t3 tHADOUT tADOUTS
DESCRIPTION ADC Clock Frequency ADC Clock Period RESSAMPLE to ADCLK RESSAMPLE to ADCONVST RESSAMPLE to ADMUX0, ADMUX1 ADOUT to ADCLK Setup ADOUT to ADCLK Hold
VALUE 8.33 120
MIN
MAX
91 40 64 19.7 2
UNITS MHz ns ns ns ns ns
Table 22: ADC Specific Timing
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31
PLL Interface Electrical Characteristics
PARAMETER Current Consumption Current Consumption Peak jitter Cycle jitter Lock-up Time PLL Reset Period SYMBOL IDDS IDD Tpj Tcj Tlock Trst CONDITION S Static Dynamic Recommended operating condition MIN -500 10 TYP 5 MAX 170 1000 +500 1 UNITS A mA ps ps ms ns
Table 23: PLL Electrical Characteristics
IRMCK201 Appendix A Host Register Map
A host computer controls the IRMCK201 using its slave-mode Full-Duplex SPI port, a standard RS-232 port or a 8-bit parallel port for connection to a microprocessor. All interfaces are always active and can be used interchangeably, although not simultaneously. Control/status registers are mapped into a 128-byte address space.
Host Parallel Access
The IRMCK201 contains an address register that is updated with the Host Register address that all subsequent data transfers are to access. This address register is updated during Host Parallel write cycles where the HPA signal is asserted to a logical high. The diagram below shows that Data Bytes 0 to N would access the register location specified by the Address Byte. The Address Bye with the HPA signal can be asserted at any time.
................
Address Byte HPA = 1
Data Byte 0 HPA = 0
Data Byte N HPA = 0
HPA = 0
Host Parallel Data Transfer Format
SPI Register Access
When configured as an SPI device read only and read/write operations are performed using the following transfer format: Command Byte Data Byte 0
................
Data Byte N
Data Transfer Format
7
Read Only
6
5
Bit Position 4 3
2
1
0
Register Map Starting Address
Command Byte Format Data transfers begin at the address specified in the command byte and proceed sequentially until the SPI transfer completes. Note that accesses are read/write unless the "read only" bit is set.
RS-232 Register Access
The IRMCK201 includes an RS-232 interface channel that allows operation using a direct connection to the host PC. This interface implements a simple protocol that checks the validity of data prior to being written into a register. The protocol is explained below. RS-232 Register Write Access A Register write operation consists of a command/address byte, byte count, register data and checksum. When the IRMCK201 receives the register data, it validates the checksum, writes the register data, and transmits and acknowledgement to the host.
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33
IRMCK201
Command / Address Byte
Byte Count
1-6 bytes of register data
Checksum
Register Write Operation
Command Acknowledgement Byte
Checksum
Register Write Acknowledgement
7
1=Read/ 0=Write
6
5
Bit Position 4 3
2
1
0
Register Map Starting Address
Command/Address Byte Format
7
1=Error/ 0=OK
6
5
Bit Position 4 3
2
1
0
Register Map Starting Address
Command Acknowledgement Byte Format The following example shows a command sequence sent from the host to the IRMCO201 requesting a two-byte register write operation: 0x2F Write operation beginning at offset 0x2F 0x02 Byte count of register data is 2 0x00 Data byte 1 0x04 Data byte 2 0x35 Checksum (sum of preceding bytes, overflow discarded) A good reply from the IRMCK201 would appear as follows: 0x2F Write completed OK at offset 0x2F 0x2F Checksum An error reply to the command would have the following format: 0xAF Write at offset 0x2F completed in error 0xAF Checksum RS-232 Register Read Access A register read operation consists of a command/address byte, byte count and checksum. When the IRMCK201 receives the command, it validates the checksum and transmits the register data to the host.
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34
IRMCK201
Command / Address Byte
Byte Count
Checksum
Register Read Operation
Command Acknowledgement Byte
Register Data
(Byte Count bytes)
Checksum
Register Read Acknowledgement (transfer OK)
Command Acknowledgement Byte
Checksum
Register Read Acknowledgement (error) The following example shows a command sequence sent from the host to the IRMCK201 requesting four bytes of read register data: 0xA0 Read operation beginning at offset 0x20 (high-order bit selects read operation) 0x04 Requested data byte count is 4 0xA4 Checksum A good reply from the IRMCK201 might appear as follows: 0x20 Read completed OK at offset 0x20 0x11 Data byte 1 0x22 Data byte 2 0x33 Data byte 3 0x44 Data byte 4 0xCA Checksum An error reply to the command would have the following format: 0xA0 Read at offset 0x20 completed in error 0xA0 Checksum RS-232 Timeout The IRMCK201 receiver includes a timer that automatically terminates transfers from the host to the IRMCK201 after a period of 32 msec. RS-232 Transfer Examples The following example shows a normal exchange executing a register write access.
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35
IRMCK201
The example below shows a normal register read access exchange.
The following example shows a register write request that is repeated by the host due to a negative acknowledgement from the IRMCK201.
In the final example, the host repeats a register read access request when it receives no response to its first attempt.
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36
IRMCK201
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37
IRMCK201
Write Register Definitions
QuadratureDecode Register Group (Write Registers)
Byte Offset 7 0x0 0x1 0x3 0x4 0x6 0x7 0x9 0xA 0xB SPARE 6 5 Bit Position 4 3
EncCntW (LSBs) (W) EncCntW (MSBs) (W) MaxEncCnt (LSBs) (W) MaxEncCnt (MSBs) (W) ZEncCnt (LSBs) (W) ZEncCnt (MSBs) (W) EncAngScl (LSBs) (W) EncAngScl (MSBs) (W) RedSig (W) PwrOn RedSig (W) ZPulse Enb (W) ZPulsePol (W) CntEnb (W)
2
1
0
QuadratureDecode Write Register Map
Field Name EncCntW MaxEncCnt
Access (R/W) W W
Field Description New value for 16-bit Quadrature Decoder counter. Maximum value of 16-bit Quadrature Decoder counter. The encoder count is reset to 0 after this count has been reached. This maximum should be set to correspond to a 360-degree physical angle. Encoder count value when the Z-pulse occurs. This value is loaded automatically in hardware when the Z-pulse occurs. (See ZPulseEnb and ZPulsePol fields below.)
ZEncCnt
W
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IRMCK201
Field Name EncAngScl Access (R/W) Field Description
CntEnb ZPulsePol ZPulseEnb
PwrOnRedSig
RedSig
This value should be set to ((MtrPoles / 2) * (4096 * 4096) / (MaxEncCnt + 1), where MtrPoles is the number of motor W poles. The value is used to convert the encoder count to an angle ranging from 0 - 4095 using the equation: Angle = ((MtrPoles / 2) * 4096 * (encoder count) / (MaxEncCnt + 1)) MOD 4096. (The current encoder count can be read from the EncCntR feld of the QuadratureDecodeStatus read register group.) W Encoder counter enable. W ZPULSE polarity. 1= load ZEncCnt on rising Z-pulse edge. 0= load ZEncCnt on falling Z-pulse edge. ZPULSE count initialization enable. When this bit is set, the W encoder count is set to the ZEncCnt value at each Z-pulse edge as determined by the ZPulsePol field. PowerOn Reduced signal enable. Set this bit in the EEPROM to enable EEPROM standalone initialization for a W wire-saving encoder. When this bit is set, the EEPROM initialization uses the PwrOnHallA, PwrOnHallB, PwrOnHallC bits instead of the HallA, HallB, HallC bits to determine initial motor angle. (The Hall bits can be read from the QuadratureDecodeStatus read register group.) W Reduced signal encoder enable. 1 = read Hall A/B/C fields from encoder A/B/Z wires. QuadratureDecode Write Register Field Definitions
PwmConfig Register Group (Write Registers)
Byte Offset 7 0xC 0xD 0xE 0xF
SPARE Gatekill Sns (W)
6
SPARE
5
Gate SnsL (W)
Bit Position 4 3
Gate SnsU (W) PwmPeriod (LSBs) (W) PwmConfig (W) PwmDeadTm (W) SPARE
2
1
SD (W)
0
SPARE
PwmPeriod (MSBs) (W)
PwmConfig Write Register Map
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IRMCK201
Field Name SD GateSnsU GateSnsL GatekillSns PwmPeriod
Access (R/W) W W W W W
Field Description
PwmConfig PwmDeadTm
W W
Shutdown control output to IR213x. Upper IGBT gate sense. 1 = active high gate control, 0 = active low gate control. Lower IGBT gate sense. 1 = active high gate control, 0 = active low gate control. GATEKILL signal sense. 1 = active high GATEKILL, 0 = active low GATEKILL. This field is used to set the desired PWM frequency using the following equation: PwmPeriod = 33,333,000 / ( 2 * (PWM frequency)) - 1, where 33,333,000 is the system clock frequency (33.333MHz). Note that while "PwmPeriod" is the name of this field, the actual PWM carrier period is 2 * (PwmPeriod + 1) * (System Clock Period = 30ns). PWM Configuration. 0 = Asymmetrical center aligned PWM, 1 = Symmetrical Center aligned PWM. Gate drive dead time in units of system clock cycles (e.g., 30 ns with 33 MHz clock). PwmConfig Write Register Field Definitions
CurrentFeedbackConfig Register Group (Write Registers)
Byte Offset 7 0x10 0x11 0x12 0x13 0x14 0x15 0x16
IfbOffsW (LSBs) (W) IfbOffsW (MSBs) (W) IdScl (LSB) (W) IdScl (MSB) (W) IqScl (LSB) (W) IqScl (MSB) (W)
6
5
Bit Position 4 3
IfbOffsV (LSBs) (W)
2
1
0
IfbOffsV (MSBs) (W)
CurrentFeedbackConfig Write Register Map
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IRMCK201
Field Name IfbOffsV Access (R/W) W Field Description
IfbOffsW
IdScl
IqScl
12-bit signed value for V phase current feedback offset. When the IfbOffsEnb bit in the SystemControl write register group is "0" this value is automatically added to each current measurement in hardware. 12-bit signed value for W phase current feedback offset. When the W IfbOffsEnb bit in the SystemControl write register group is "0" this value is automatically added to each current measurement in hardware. Rotating frame Id component current feedback scale factor. Constant W used to scale current measurements before they are used in the field orientation calculation. This is a 15-bit fixed-point signed number with 10 fractional bits that ranges from -16 to + 16 + 1023 / 1024. Rotating frame Iq component current feedback scale factor. Constant W used to scale current measurements before they are used in the field orientation calculation. This is a 15-bit fixed-point signed number with 10 fractional bits that ranges from -16 to + 16 + 1023 / 1024. CurrentFeedbackConfig Write Register Field Definitions
SystemControl Register Group (Write Registers)
Byte Offset 7 0x17
DcComp Enb
6
IfbOffs Enb
5
Bit Position 4 3
SPARE
2
Reserved
1
Foc EnbW
0
Pwm EnbW
SystemControl Write Register Map
Field Name PwmEnbW
Access (R/W) W
Field Description PWM Enable bit. Setting this bit to 1 or 0 sets the IGBT gate control signals to their active or inactive states. At power up the gate control output signals remain in a high-Z state. After PwmEnbW is set for the first time, the gate controls are driven to their active or inactive states according to the value of PwmEnbW. A fault condition clears this bit automatically in hardware. Field Orientated Control Enable bit. Setting this bit to 1 enables the FOC algorithm. Setting this bit to 0 resets the FOC algorithm and causes zero output voltage to be applied to the motor. A fault condition clears this bit automatically in hardware. This field should is reserved and should be set to 0.
FocEnbW
W
Reserved
W
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IRMCK201
Field Name Access (R/W) Field Description
IfbOffsEnb
DcCompEnb
When IFB PwmEnbW = 1, and FocEnbW = 0, the Current feedback offset is calculated and saved in the CurrentFeedbackOffset read register group. When IfbOffsEnb = 1, the Current feedback offset W values in the CurrentFeedbackOffset Read registers are applied to each current feedback measurement. When IfbOffsEnb = 0, the Current feedback offset values in the CurrentFeedbackConfig Write registers are applied to each current feedback measurement. DC Bus Compensation enable. When this bit is set to "1", PWM output is compensated for using the following formula: W PWM (comp) = PWM * 310 / DCBUSVOLTS where PWM (comp) is the compensated PWM output voltage; PWM is the uncompensated PWM output voltage; 310 is the nominal DC bus voltage; and DCBUSVOLTS is the actual DC bus voltage. SystemControl Write Register Field Definitions
CurrentLoopConfig Register Group (Write Registers)
Byte Offset 7 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 6 5 Bit Position 4 3
2
(LSBs)
1
0
IqRefW - Quadrature Reference Current (W)
IqRefW - Quadrature Reference Current (MSBs) (W) KpIreg - Current Loop Proportional Gain (LSBs) (W) KpIreg - Current Loop Proportional Gain (MSBs) (W) KxIreg - Current Loop Integral Gain (LSBs) (W) KxIreg - Current Loop Integral Gain (MSBs) (W) IdRef - Direct/Magnetizing Reference Current (W) (LSBs)
IdRef - Direct/Magnetizing Reference Current (MSBs) (W) SlipGn (LSBs) (W) SlipGn (MSBs) (W) VqLim - Quadrature Current Output Limit (LSBs) (W) VqLim - Quadrature Current Output Limit (MSBs) (W)
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IRMCK201
Byte Offset 7 0x26 0x27 6 5 Bit Position 4 3 2 1 0
VdLim - Direct Current Output Limit (LSBs) (W) VdLim - Direct Current Output Limit (MSBs) (W)
CurrentLoopConfig Write Register Map
Field Name IqRefW KpIreg KxIreg IdRef SlipGn VqLim VdLim
Access (R/W) W W W W W W W
Field Description 15-bit signed quadrature current reference input from velocity loop. 15-bit signed current loop PI controller proportional gain. Scaled with 14 fractional bits for an effective range of 0 - 1. 15-bit signed current loop PI controller integral gain. Scaled with 19 fractional bits for an effective range of 0 - .03125. 15-bit signed direct/magnetized current to D-axis current loop PI controller. This parameter controls the slip speed for induction motor applications. SlipGn should be set to 2048 * 2048 * (Rated slip speed in Hz) / (Current loop update frequency). SlipGn MUST be set to 0 if slip is not desired. 16-bit Quadrature current PI controller voltage output limit. 16-bit Direct current PI controller voltage output limit. CurrentLoopConfig Write Register Field Definitions
VelocityControl Register Group (Write Registers)
Byte Offset 7 0x31 0x32 0x33 0x34 0x35 0x36 0x37 6
SPARE
5
Bit Position 4 3
2
SpdLpRate
1
0
SpdLpEnb
KpSreg - Velocity loop proportional gain (LSBs) (W) KpSreg - Velocity loop proportional gain (MSBs) (W) KxSreg - Velocity loop integral gain (LSBs) (W) KxSreg - Velocity loop integral gain (MSBs) (W) SregLimP - Velocity loop positive Limit (LSBs) (W) SregLimP - Velocity loop positive Limit (MSBs) (W)
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IRMCK201
Byte Offset 7 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 6 5 Bit Position 4 3 2 1 0
SregLimN - Velocity loop negative Limit (LSBs) (W) SregLimN - Velocity loop negative Limit (MSBs) (W) SpdScl - Speed Scale Factor (LSBs) SpdScl - Speed Scale Factor (MSBs) TargetSpd - Setpoint/target speed (LSBs) TargetSpd - Setpoint/target speed (MSBs) SpdAccRate - Acceleration SpdDecRate - Deceleration
VelocityControl Write Register Map
Field Name SpdLpEnb SpdLpRate KpSreg KxSreg SregLimP SregLimN SpdScl TargetSpd SpdAccRate SpdDecRate
Access (R/W) W W W W W W W W W W
Field Description
Speed loop enable: 1 = enable speed loop PI controller. 0 = Reset Speed loop PI controller. Speed loop update rate: 0 = disabled, N = update speed loop immediately before every Nth current loop update. 15-bit velocity loop proportional gain, in fixed point with 5 fractional bits. Range = 0 - 512. 15-bit velocity loop integral gain, in fixed point with 13 fractional bits. Range = 0 - 2. 16-bit speed PI controller output positive limit. 16-bit speed PI controller output negative limit (2's complement). Motor Speed Scale factor. The user should set SpdScl = 60 * 16383 * (33.333MHz/32) / (Max RPM * Encoder PPR) / 2, which will result in a Speed value ranging 16384 corresponding to Max RPM. Velocity loop speed setpoint in SPEED units, which are determined by the user via the SpdScl register setting. Velocity loop acceleration in units of SPEED / Velocity loop execution or SPEED / (SpdLpRate / PWM period). Velocity loop deceleration in units of SPEED / Velocity loop execution or SPEED / (SpdLpRate / PWM period). VelocityControl Write Register Field Definitions
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IRMCK201
FaultControl Register Group (Write Registers)
Byte Offset 7 0x42 6 5
SPARE
Bit Position 4 3
2
1
FltClr
0
DcBusM Enb
FaultControl Write Register Map
Field Name
Access (R/W)
Field Description DC Bus monitor enable. 1 = Monitor DC bus voltage and generate appropriate brake signal control and disable PWM output when voltage fault conditions occur. GatekillFlt and OvrSpdFlt faults cannot be disabled. DC bus voltage thresholds are as follows: Overvoltage - 410V Brake On - 380V Brake Off - 360V Nominal - 310V Undervoltage off - 140V Undervoltage - 120V This bit clears all active fault conditions. The user should monitor the FaultStatus read register group to determine fault status and set this bit to "1" to clear any faults that have occurred. A fault condition automatically clears the PwmEnbW and FocEnbW bits in the SystemControl write register group. Note that this bit also directly controls the output 2137 FLTCLR pin. After clearing a fault, the user must explicitly set this bit to "0" to re-enable fault processing. FaultControl Write Register Field Definitions
DcBusMEnb
W
FltClr
W
SVPWMScaler Register Group (Write Registers)
Byte Offset 7 0x44 0x45 6 5 Bit Position 4 3
ModScl (LSBs) (W) ModScl (MSBs) (W)
2
1
0
SVPWMScaler Write Register Map
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IRMCK201
Field Name ModScl
Access (R/W)
Field Description
Space vector modulator scale factor. This register, which depends on the PWM carrier frequency, should be set as follows: W ModScl = PwmPeriod * sqrt(3) * 4096 / 2355 where PwmPeriod is the value in the PwmConfig write register group's PwmPeriod register. SVPWMScaler Write Register Field Definitions
DiagnosticPwmControl Register Group (Write Registers)
Byte Offset 7 0x4E 0x4F 6 5
PwmData1Sel PwmData3Sel
Bit Position 4 3
2
1
0
PwmData0Sel PwmData2Sel
DiagnosticPwmControl Write Register Map
Field Name
Access (R/W)
Field Description
PwmData0Sel, PwmData1Sel, PwmData2Sel, PwmData3Sel
Selects diagnostic data items for output on DAC PWM pins 0-3. These pins are intended for use with external RC filters for oscilloscope diagnostic display: 1 = DC Bus Voltage 2 = V phase current 3 = W phase current 5 = Speed PI Reference W 6 = Speed PI Feedback 7 = Speed PI Error 8 = IQ Ref 9 = Q axis voltage Qv 10 = D axis voltage Dv 11 = 12-bit electrical angle 12 = Q axis current Qi 13 = D axis current Di 14 = A axis (stationary frame) voltage Av 15 = B axis (stationary frame) voltage Bv DiagnosticPwmControl Write Register Field Definitions
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IRMCK201
SystemConfig Register Group (Write Registers)
Byte Offset 7 0x50
ExtCtrlW
6
SpdRefSel
5
Bit Position 4 3
IqRefSel
2
HostAng Enb
1
HostVd Enb
0
RmpRef Sel
SystemConfig Write Register Map
Field Name RmpRefSel HostVdEnb
Access (R/W) W W
Field Description
HostAngEnb IqRefSel
W W
SpdRefSel
W
ExtCtrlW
W
Speed Ramp reference select. 0= TargetSpd field of the VelocityControl write register group, 1 = External analog reference. Host D-Axis current control enable. When this bit is set, the D-Axis PI Controller is disconnected from the forward path vector rotator, which then takes its input from the VdSfwd field of the DirectHostVoltageControl write register group. Host electrical angle control enable. When this bit is set, the vector rotator takes its angle input from the ElecAngW field of the DirectHostVoltageControl write register group. Selects the source for the Q-Axis PI controller IQREF input: 0 = Speed PI controller output 1 = IqRefW field of the CurrentLoopConfig write register group 2 = Reference A/D converter input. Selects the source for the Speed PI controller reference input: 0 = Internal Accel/Deccel ramp generator 1 = TargetSpd field of the VelocityControl write register group 2 = Reference A/D converter input. Setting this bit to "1" enables direct control of basic motor operation via the external User Interface pins. When this bit is "1", the FocEnbW and PwmEnbW bits in the SystemControl write register group are ignored. SystemConfig Write Register Field Definitions
DirectHostVoltageControl Register Group (Write Registers)
Byte Offset 7 0x52 0x53
VqSfwd (LSBs) (W)
6
5
Bit Position 4 3
VdSfwd (LSBs) (W)
2
1
0
VdSfwd (MSBs) (W)
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IRMCK201
Byte Offset 7 0x54 0x55 0x56
SPARE
6
5
Bit Position 4 3
VqSfwd (MSBs) (W) ElecAngW (LSBs) (W)
2
1
0
ElecAngW (MSBs) (W)
DirectHostVoltage Control Write Register Map
Field Name VdSfwd VqSfwd ElecAngW
12-bit signed value for synchronous frame direct current when host direct current control is enabled. This field is typically used for V/Hz control. W 12-bit signed value for synchronous frame quadrature voltage that is added to the Q-Axis PI-controller output. This field is typically used for feedforward or V/Hz control. W 12-bit electrical angle used when host electrical angle control is enabled. This field is typically used for V/Hz control. DirectHostVoltageControl Write Register Field Definitions
Access (R/W) W
Field Description
32bitQuadDecode Register Group (Write Registers)
Byte Offset 7 0x58 0x59 0x5A 0x5B 6 5 Bit Position 4 3
EncCnt32bW (bits 0-7) (W) EncCnt32bW (bits 8-15) (W) EncCnt32bW (bits 16-23) (W) EncCnt32bW (bits 24-31) (W)
2
1
0
32bitQuadDecode Write Register Map
Field Name EncCnt32bW
Access Field Description (R/W) W New value for 32-bit Quadrature Decoder counter. 32bitQuadDecode Write Register Field Definitions
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IRMCK201
EepromControl Registers (Write Registers)
At power up, the write registers can be optionally initialized with values stored in EEPROM. The EepromControl write register group and EepromStatus read register group are used to read and write these EEPROM values. Since the EeAddrW write register (which selects the EEPROM offset to read or write) does not require initialization at power up, the location corresponding to that register in EEPROM (at offset 0x5D) is used to store a register map version code. At power on, the FPGA initializes the write registers from EEPROM only if the version code stored at this offset in EEPROM matches its internal register map version code (which can be read from the RegMapVer field of the EepromStatus read register group). To enable write register initialization at power up, write the appropriate register map version code to EEPROM at offset 0x5D. To disable write register initialization at power up, write a zero (or any non-matching version code) to offset 0x5D of the EEPROM. Byte Offset 7 0x5C 0x5D 0x5E 6 5
SPARE EeAddrW / RegMapVersCode (W) EeDataW (W)
Bit Position 4 3
2
EeWrite
1
EeRead
0
EeRst
EepromControl Write Register Map
Field Name EeRst EeRead
Access (R/W) W W
Field Description
EeWrite EeAddrW EeDataW
W W W
Self-clearing EEPROM reset. Writing a "1" to this bit resets the I2C EEPROM interface. Self-clearing I2c EEPROM Read. Writing a "1" to this bit initiates an EEPROM read from the byte located at EEPROM address EeAddrW. After setting this bit the user should poll the EeBusy bit in the EepromStatus read register group to determine when the read completes and then read the data from EeDataR in the EepromStatus read register group. Self-clearing EEPROM Write. Writing a "1" to this bit initiates an EEPROM write from the data byte in EeDataW to the EEPROM address EeAddrW. EEPROM Address Register. Contains the address for the next EEPROM read or write operation. EEPROM Data Register. Contains the data for the next EEPROM write operation. EepromControl Write Register Field Definitions
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IRMCK201
HallSensorEncoderInit (Write Registers - EEPROM only)
These values must be set in the EEPROM for initial encoder count/angle initialization in the EEPROM standalone (i.e. operation without a host program). EEPROM initialization logic automatically loads the appropriate value into the encoder counter at power-on based on the HALL A/B/C sensor values. These values are present only in the EEPROM since they serve no purpose after power on. Byte Offset 7 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 6 5 Bit Position 4 3
HallCBA001(LSBs) HallCBA001(MSBs) HallCBA010 (LSBs) HallCBA010 (MSBs) HallCBA011(LSBs) HallCBA011(MSBs) HallCBA100 (LSBs) HallCBA100 (MSBs) HallCBA101(LSBs) HallCBA101(MSBs) HallCBA110 (LSBs) HallCBA 110 (MSBs)
2
1
0
HallSensorEncoderInit Register Map
Field Name HallCBAnnn
Access (R/W) W (EEPROM ONLY)
Field Description Initial encoder count for Hall Sensor [C, B, A] value [n, n, n]. HallSensorEncoderInit Field Definitions
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IRMCK201
Read Register Definitions
QuadratureDecodeStatus Register Group (Read Registers)
Byte Offset 7 0x0 0x1 0x3
SPARE PwrOn HallC PwrOn HallB
6
5
Bit Position 4 3
EncCntR (LSBs) (R) EncCntR (MSBs) (R) PwrOn HallA SPARE
2
1
0
HallC
HallB
HallA
QuadratureDecodeStatus Read Register Map
Field Name EncCntR HallA, HallB, HallC PwrOnHallA, PwrOnHallB, PwrOnHallC
Access (R/W) R R R
Field Description Current value of 16-bit Quadrature Decoder counter. Hall Sensor A/B/C values. Hall Sensor A/B/C values at power-on for reduced-wire encoder interface.
QuadratureDecodeStatus Read Register Field Definitions
SystemStatus Register Group (Read Registers)
Byte Offset 7 0x7 0x8 0x9
Start
6
Stop
5
SPARE
Bit Position 4 3
PwrID RevCode (LSBs) RevCode (MSBs)
2
GateKill
1
Foc EnbR
0
Pwm EnbR
SystemStatus Read Register Map
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IRMCK201
Field Name PwmEnbR FocEnbR GateKill PwrID Stop Start RevCode Access (R/W) R R R R R R R Field Description
PWM Enable bit status. FOC Enable bit status. GATEKILL status. This bit is set by the Gatekill input from the IR2137. Once set, this bit remains set until it is cleared by writing a "1" to the FaultClr bit in the FaultControl write register group. Power ID. 0 = 3 kW, 1 = 2 kW, 2 = 500 W. User Interface "STOP" digital input status. User Interface "START" digital input status. IC Revision Code. Revision code format is "XX.XX", where each "X" is a 4-bit hexadecimal number. SystemStatus Read Register Field Definitions
DcBusVoltage Register Group (Read Registers)
Byte Offset 7 0xA 0xB
SPARE
6
5
Bit Position 4 3
DcBusVolts (LSBs) Brake
2
1
0
DcBusVolts (MSBs)
DcBusVoltage Read Register Map
Field Name DcBusVolts Brake
Access (R/W) R R
Field Description
DC Bus Voltage. Data range is 0 - 4095, which corresponds to a DC bus voltage between 0 and 500 volts. Brake signal status. 0 = Brake signal active. DcBusVoltage Read Register Field Definitions
FocDiagnosticData Register Group (Read Registers)
Byte Offset 7 0xC 0xD 6 5 Bit Position 4 3
2
1
0
IvFbk - V Phase IFB Raw Current (LSBs) (R) IwFbk - W Phase IFB Raw Current (LSBs) (R) IvFbk - V Phase IFB Raw Current (MSBs) (R)
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
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IRMCK201
Byte Offset 7 0xE 0xF 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 6 5 Bit Position 4 3 2 1 0
IwFbk - W Phase IFB Raw Current (MSBs) (R) Id - Synchronous Frame Direct Current (LSBs) (R) Id - Synchronous Frame Direct Current (MSBs) (R) Iq - Synchronous Frame Quadrature Current (LSBs) (R) Iq - Synchronous Frame Quadrature Current (MSBs) (R) Ud - Synchronous Frame Direct Voltage (LSBs) (R) Ud - Synchronous Frame Direct Voltage (MSBs) (R) Uq - Synchronous Frame Quadrature Voltage (LSBs) (R) Uq - Synchronous Frame Quadrature Voltage (MSBs) (R) UAlpha - Stationary Frame Alpha Voltage (LSBs) (R) UBeta - Stationary Frame Beta Voltage (LSBs) (R) UAlpha - Stationary Frame Alpha Voltage (MSBs) (R)
UBeta - Stationary Frame Beta Voltage (MSBs) (R)
FocDiagnosticData Read Register Map
Field Name IvFbk, IwFbk
Access (R/W) R
Field Description Offset-corrected V and W phase raw current from the IR2175 current sensor. Values range from 0 - 4096, where 2048 corresponds to 0 current. The current feedback scale factors IdScl and IqScl in the CurrentFeedbackConfig write register group and the current sense resistor value determine the full scale current value. Synchronous or rotating frame direct and quadrature current values in 2's complement representation. The full scale current values range from -16384 to 16383. Synchronous or rotating frame direct and quadrature voltage values in 2's complement representation. Data ranges are VdLim for Ud and VqLim for Uq as specified in the CurrentLoopConfig write register group.
Id, Iq Ud, Uq
R R
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IRMCK201
UAlpha, UBeta R Stationary frame Alpha and Beta voltage output component values. Data range is VdLim or VqLim (as specified in the CurrentLoopConfig write register group), whichever is larger. FocDiagnosticData Read Register Field Definitions
FaultStatus Register Group (Read Registers)
The Fault Status register records fault conditions that occur during drive operation. When any of these fault conditions occur, the PWM output is automatically disabled. The user should monitor this register continuously for fault conditions. A fault condition can be cleared by writing a "1" to the FaultClr bit in the FaultControl write register group. (This does not automatically re-enable PWM output.) Byte Offset 7 0x1E 6
SPARE
5
Bit Position 4 3
ExecTm Flt OvrSpdFlt
2
OvFlt
1
LvFlt
0
GatekillFlt
FaultStatus Read Register Map
Field Name GatekillFlt LvFlt OvFlt
Access (R/W) R R R
Field Description Filtered and latched version of IR213x FAULT output. DC bus low voltage fault. This fault occurs if the DC bus drops below 120V. DC bus overvoltage fault. This fault occurs if the DC bus voltage exceeds 410V. Over speed fault. This fault occurs whenever the motor reaches the positive or negative limits. The user should use the scale factor in the SpdScl field of the VelocityControl write register group to scale the motor speed so that it falls between -16384 and +16383 with these limits as the over speed condition. Execution time fault. FaultStatus Read Register Field Definitions
OvrSpdFlt ExecTmFlt
R R
VelocityStatus Register Group (Read Registers)
Byte Offset 7 0x26 0x27 6 5 Bit Position 4 3
Spd (LSBs) Spd (MSBs)
2
1
0
VelocityStatus Read Register Map
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
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IRMCK201
Field Name Spd
Access (R/W) R
Field Description
Current motor speed in SPEED units. (See the description of SpdScl in the VelocityControl write register group.) VelocityStatus Read Register Field Definitions
CurrentFeedbackOffset Register Group (Read Registers)
Byte Offset 7 0x30 0x31 0x32
IfbWOffs (LSBs) (R) IfbWOffs (MSBs) (R)
6
5
Bit Position 4 3
IfbVOffs (LSBs) (R)
2
1
0
IfbVOffs (MSBs) (R)
CurrentFeedbackOffset Read Register Map
Field Name IfbVOffs, IfbWOffs
Access (R/W) R
Field Description
Current feedback offset values from the last IFB Offset calculation. These values are automatically applied to each current feedback measurement value whenever the IfbOffsEnb bit in the SystemControl write register group is set. CurrentFeedbackOffset Read Register Field Definitions
32bitQuadDecodeStatus Register Group (Read Registers)
Byte Offset 7 0x34 0x35 0x36 0x37 6 5 Bit Position 4 3
EncCnt32bR (bits 0-7) (R) EncCnt32bR (bits 8-15) (R) EncCnt32bR (bits 16-23) (R) EncCnt32bR (bits 24-31) (R)
2
1
0
32bitQuadDecodeStatus Read Register Map
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IRMCK201
Field Name EncCnt32bR
Access Field Description (R/W) R Current value of 32-bit Quadrature Decoder counter. 32bitQuadDecodeStatus Read Register Field Definitions
EepromStatus Registers (Read Registers)
Byte Offset 7 0x38 0x39 0x3A 0x3B 6 5 Bit Position 4 3
SPARE EeDataR (R) EeAddrR (R) RegMapVer (R)
2
1
0
EeBusy
EepromStatus Read Register Map
Field Name EeBusy EeDataR EeAddrR
Access (R/W) R
Field Description
RegMapVer
I2C EEPROM Interface busy bit. The user should wait for this bit to clear before initiating EEPROM read or write operations. R EEPROM Data Register. Contains the data from the last EEPROM read operation. Note that writing to the EeRst field in the EepromControl write register group invalidates this register. R EEPROM Address read register shows the value stored in EEPROM at the offset of the EeAddrW write register (0x5D). Since this address in the EEPROM contains the BPFPGA register map version, the user can read this field to determine whether or not the write registers were initialized at power on. R Current register map version code. EepromStatus Read Register Field Definitions
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IRMCK201
FOCDiagnosticDataSupplement Register Group (Read Registers)
Byte Offset 7 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43
SPARE SpdRef (LSBs) (R) SpdRef (MSBs) (R) SpdErr (LSBs) (R) SpdErr (MSBs) (R) IqRefR (LSBs) (R) IqRefR (MSBs) (R)
6
5
Bit Position 4 3
ElecAngR (LSBs) (R)
2
1
0
ElecAngR (MSBs) (R)
FOCDiagnosticDataSupplement Read Register Map
Field Name ElecAngR SpdRef SpdErr IqRefR
Access Field Description (R/W) R Electrical angle. R Speed PI controller reference input. R Speed PI controller error. R Speed PI controller output. FOCDiagnosticDataSupplement Read Register Field Definitions
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IRMCK201 Appendix B Package
HD D
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 49 48 47 46 45 44 43 42 41
QFP100
40 39 38 37 36 35 34 33 32 31 30 29 28
E
HE
INDEX
27 26
17
18
19
22
23
24
10
11
12
13
14
15
16
20
e
b
A
O2 R 1 R
A2 L2 L1
21
25
1
2
3
4
5
6
7
8
9
A1
O3
L
Table 24: QFP100 Package
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
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IRMCK201
DIMENSION IN MILIMETERS SYMBOL Min. E D A A1 A2 e b C L L1 L2 HE HD O2 O3 R R1 15.6 15.6 0.13 0.1 0 0.3 0.5 1 0.5 16 16 12 12 0.2 0.2 16.4 16.4 1.3 0.1 1.4 0.5 0.18 0.125 0.28 0.175 10 0.7 1.5 13.9 13.9 Nom. 14 14 Max. 14.1 14.1 1.7
DIMENSION IN INCHES* Min. (0.548) (0.548) Nom. (0.551) (0.551) Max. (0.555) (0.555) (0.066) (0.004) (0.052) (0.055) (0.020) (0.006) (0.004) (0) (0.012) (0.20) (0.039) (0.020) (0.615) (0.615) (0.630) (0.630) (12) (12) (0.008) (0.008) (0.645) (0.645) (0.007) (0.005) (0.011) (0.006) (10) (0.027) (0.059)
Table 25: QFP100 Dimensions
* For reference
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IRMCK201 Appendix C
1. 2.
Errata
Using the ADS7818 A/D converter interface as the current feedback source is not supported The scaling is too large by a factor of 16 for the following Diagnostic DAC PWM selections: Reference Speed (PWM data select value of 5), Motor Speed (PWM data select value of 6), IQREF (PWM data select value of 8). The scaling is too large by a factor of 8 for the following Diagnostic DAC PWM selections: IQ (PWM data select value of 12), ID (PWM data select value of 13). The scaling is too large by a factor of 4 for the following Diagnostic DAC PWM selections: Av (PWM data select value of 14), Bv (PWM data select value of 15). These values will work at small data ranges, but overflow otherwise. use the parallel port and diagnostic data registers. To extract the correct data for these items,
3.
When the IRMCK201 is implemented in conjunction with the ADS7818, note that the IRMCK201 ADCLK is specified at 120 ns while the ADS7818 is specified at 125 ns.
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IRMCK201
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 http://www.irf.com Data and specifications subject to change without notice. 9/15/2003
Sales Offices, Agents and Distributors in Major Cities Throughout the World.
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61

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